帮写ENEE640 Exam 1代做Matlab编程
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Due Midnight 03/27/2024
1 Problem Statement
In this exam, you will design a combinational sorting circuit. The sorting circuit should take eight unsigned 4-bit numbers X0..X7 as inputs and produce the same eight 4-bit numbers in ascending order as outputs Y0..Y7. For instance, if the inputs are
{X0,X1,X2,X3,X4,X5,X6,X7} = {2,7,5,15,9, 10,13,4}, then the outputs are
{Y0,Y1,Y2,Y3,Y4,Y5,Y6,Y7} = {2,4,5,7,9,10,13,15}. Since each input is 4 bits, your circuit will have a total of 32 digital inputs and 32 digital outputs as shown in Fig. 1 (4 bits for each of the eight input numbers).
In this exam, you will perform. the following steps:
1. Schematic Design. You should draw a transistor level schematic of a circuit that implements the functionality of the described sorting circuit. You are free to implement this circuit using any circuit topology and any optimization techniques you see fit (note that your circuit must be combinational, and thus should not use any sequential logic/clocked memory). Hierarchical design is highly recommended.
2. Functionality Test. You shall use Spectre simulation environment to simulate your design. To verify the I/O behavior. of your design, you shall simulate your circuit using a set of voltage sources we provide you that implement a set of test cases. You will export the input and output signals from your designs using the Cadence Waveform. Tool as CSV files. A MATLAB function sorter_check will be provided to check these waveforms to determine whether the circuit is performing the correct functionality.
3. Performance Analysis. You will also calculate the power and worst-case propagation delay to characterize the performance of your design. This can easily be accomplished using the Waveform Viewer after simulating your circuit with Spectre and another MATLAB function power_calc we provide.
Note: VDD in this exam is 3V. You may not change VDD. You also may not change the threshold voltages of the transistors.
Figure 1: Pin Names and Example I/O of the Sorting Circuit.
More details on Steps 2 and 3 will be discussed in the section below.
2 Functionality Verification
In order to verify your design, please carefully follow the instructions given in this section. We will explain how to generate test vectors, how to export signals and how to run our scripts.
2.1 Test Vector Generation
We use the following notation for inputs and outputs of your circuit. Please use the following pin names in your design (also see Fig. 1).
• Let X7, X6, X5, X4, X3, X2, X1, and X0 be the eight 4-bit inputs of the sorting circuit. Please name your input pins:
X7_3, X7_2, X7_ 1, X7_0,
X6_3, X6_2, X6_ 1, X6_0,
X5_3, X5_2, X5_ 1, X5_0,
X4_3, X4_2, X4_ 1, X4_0,
X3_3, X3_2, X3_ 1, X3_0,
X2_3, X2_2, X2_ 1, X2_0,
X1_3, X1_2, X1_ 1, X1_0,
X0_3, X0_2, X0_ 1, X0_0,
where X0_0 is the least significant bit (LSB) of X0, and X0_3 is the most significant bit (MSB) of X0.
• Let Y7, Y6, Y5, Y4, Y3, Y2, Y1, and Y0 be the eight 4-bit outputs of the sorting circuit. Please name your output pins:
Y7_3, Y7_2, Y7_ 1, Y7_0,
Y6_3, Y6_2, Y6_ 1, Y6_0,
Y5_3, Y5_2, Y5_ 1, Y5_0,
Y4_3, Y4_2, Y4_ 1, Y4_0,
Y3_3, Y3_2, Y3_ 1, Y3_0,
Y2_3, Y2_2, Y2_ 1, Y2_0,
Y1_3, Y1_2, Y1_ 1, Y1_0,
Y0_3, Y0_2, Y0_ 1, Y0_0,
where Y0_0 is the least significant bit (LSB) of Y0, and Y0_3 is the most significant bit (MSB) of Y0.
To test your design, we will need to generate test vectors. Usually when designing a large circuit, the number of inputs is huge and it would be computationally infeasible to exhaustively check all unique combinations of inputs. As a result, designers usually use a set of test cases that stresses the extreme cases of the design to verify that it functions correctly. The inputs used in these test cases are called test vectors. Thus, we will provide you with 64 test vectors to test your design on (see test_vectors.txt). These test vectors are represented as piecewise-linear (PWL) voltage sources in Spectre. Please copy all the statements in test_vectors.txt to the Spectre Source Statements section of your simulation script (si.inp), right below the line “// Spectre Source Statements”.
2.2 Exporting Signals as a CSV File
The I/O signals of your design can be exported as follows. After simulating your design using Spectre, view the results using the Waveform. tool. In the results browser, highlight all of the input and output voltage signals of the design. This can be accomplished by holding the control key and clicking each signal with the mouse. Then right click the selected signals and choose the Export option. In the Export Waveforms window, select a directory, name the output file, and save as CSV type.
In order to verify the functionality, we will use this CSV as input to MATLAB. It is important that you highlight and save all the signals as one file as discussed above. Note that there are various ways to retrieve your files from the glue server for input to MATLAB. A valid option for Windows is to use the WinSCP program, or FileZilla for any operating system. Alternatively, you could also use MATLAB directly on the glue server (i.e. tap matlab and follow the instructions).
2.3 Running Our MATLAB Script.
The sorter_check.m file contains the function sorter_check, which is used to digitize the signals in your CSV file and verify the correct I/O behavior. The inputs to the function sorter_check areas follows:
• The name of the CSV file you obtained in Section 2.2.
• The voltage value corresponding to a logic 1 in your design. For the TSMC02 technology node, this should be 3.
The output will be a pass/fail message. If your schematic fails the functionality test, the input combinations that results in erroneous output are also indicated in the message.
Note that you must follow the above instructions exactly in order to verify your designs (especially pay attention to the naming convention above). If you are having trouble, please contact the TA for assistance. You can also retrieve additional information about using the sorter_check function by typing “help sorter_check” in the MATLAB command window.
3 Calculation of Power and Delay
Faster digital circuits usually require greater power. Thus, propagation delay and power consumption generally form a design trade-off. In this exam, you will measure the average power across the test vectors provided, and the worst case delay. We will not attempt to combine power and delay into a single metric, but rather will consider both metrics independently such that a design is considered optimal if no other design has both smaller delay and lower power (i.e. if the design is Pareto optimal). Instructions on how to determine power and delay for your sorting circuit is discussed in the subsections below.
3.1 Power Calculation Method
Average power (Pavg) is calculated as:
where Psupply(t) is the power from the supply at time t and T is the length of the experiment. In this exam, you will feed each input case to your circuit and record the Psupply(t) signal in Spectre. In order to save Psupply(t), you must include “save :pwr” command in the “Output Options” section of your simulation script (si.inp), right below the line “//Output Options”. Then a power signal will appear in the results browser of the Waveform tool after successful simulation. In order to calculate the average power (Pavg), we need you to extract the power signal as a new CSV file (see Section 2.2) and use it as input to a MATLAB function we provide called power_calc. When you run thepower_calc function on your power signal CSV file, your output will be in Joules (energy). To convert to power in Watts, you should divide by the total simulation time (640ns). You can retrieve instructions on using the power_calc function by typing “help power_calc” in the MATLAB command window.
3.2 Delay Calculation Method
For the worst case delay, you can assume that it is the propagation delay in the following transition of inputs: {X0,X1,X2,X3,X4,X5,X6,X7} = {0,0,0,0,0,0,0,0} to
{X0,X1,X2,X3,X4,X5,X6,X7} = {15, 14, 13,12, 10,5,3,0}. You can obtain the delay manually by viewing the output waveforms for this transition in Spectre and measuring when the outputs reach VDD/2. Alternatively, the propagation delay can also be calculated using the
Calculator tool (i.e. see special function delay in the Calculator tool). The worst-case delay is defined as the maximum propagation delay across all circuit outputs when simulating this transition.
When viewing the output waveforms after simulating your circuit, it is possible that you may have outputs that look like this (yellow curve):
These are called “glitches”, and they occur when some signals arrive at gates faster than other signals and cause the output to temporarily goto ground or VDD before switching to the correct value. If your design has glitches, the propagation delay for each signal will be the time it takes to reach VDD/2 after all the glitches have settled down.
4 Instructions for Report
You should submit a detailed report about your experiences in this exam and your results.
Your report must contain the following contents (and you may add your own ass you see fit):
• Abstract
• Introduction: Discuss the background and motivation for your design, a snippet of your results and the main conclusions you’ve reached.
• Design: You should have a discussion on the optimized design you’ve implemented in this section (including appropriate figures of schematics, etc.). Please describe all the techniques you have implemented in detail (the intuition behind the technique and what behavior. you are expecting). Please also describe in detail how your circuit sorts the input numbers.
• Results and Discussion: In this section, you should provide the power and delay of your circuit. Please provide a screenshot of the output delay when simulating the worst-case transition. Finally, some discussions on possible design alternatives to improve power or delay (at the expense of the other metric) would be a plus. Please share any intuition you have gained from this project regarding circuit optimization techniques.
• Conclusion
• References: Please cite other people’s work properly.
5 Deliverables
Please submit the following materials:
• The CSV files containing the signals from simulations of your schematic using the
provided voltage source test vectors. Please name the file “ <your-last-name>_IO.csv” (without the brackets). We shall use these to verify the functionality of your schematics.
• The CSV files containing the power signal from the simulation. Please name this file
“
• A screenshot of the worst-case delay.
• The report.
6 Attachments
The following files have been attached:
• test_vectors.txt: voltage sources for test vectors
• sorter_check.m: MATLAB function sorter_check which verifies the functionality of your design.
• power_calc.m: MATLAB function power_calc which calculates the average power consumption of your design.
7 Grading
The functionality, delay, power, and the report will all betaken into consideration. There will be a total of 200 points which are split into 3 parts:
• Correct functionality: 40 points
• Power-delay trade-off: 140 points. As mentioned earlier, we consider the Pareto optimality of the designs. All the optimal designs will receive full points. Other designs will receive grades based on the ‘closest’ optimal design. Formally, the grade of a design is
where f is the grading function based on the power and the delay, (p,d) is the power and delay of a design, and Dopt is the set of optimal designs.
Note: Please do not modify VDD!
• The report: 20 points