代做EEC 180 — DIGITAL SYSTEMS II WINTER QUARTER — 2022 MIDTERM EXAM代做回归

EEC 180 — DIGITAL SYSTEMS II

WINTER QUARTER — 2022 — 5 UNITS

MIDTERM EXAM

1  CIRCUIT MODELING (25 POINTS)

Consider the circuit below with seven inputs and a single output.

Write a Verilog model for the above circuit.

2  COUNTERS (25 POINTS)

Consider a counter with the following specifications:

• The counter has two synchronous inputs RESET and M.

• If RESET =  1,  the counter resets the  state to  1.  Otherwise, the  state  is updated according to the value of M.

•   If M = 0, the counter counts 1, 2, 3, 4, 5, 6, and repeat.

•   If M = 1, the counter counts 6, 5, 4, 3, 2, 1, and repeat.

Write a Verilog model for the counter. Assume that it is the responsibility of the user of the counter to reset it before using it.

3  BIT WIDTH (15 + 10 = 25 POINTS)

1.  Suppose that we want to add eight n-bit signed (two’s complement) numbers. How many bits are needed for the sum so that no overflow will occur.

2. Using your result from above, write a Verilog model for a combinational circuit that adds eight 5-bit signed numbers.

4  CIRCUIT MODELING (25 POINTS)

Consider the implementation shown below.

Develop a Verilog model for the above circuit using no more than two assign statements.

5  COMBINATIONAL ARITHMETIC CIRCUITS (10 + 5 + 10 = 25 POINTS)

Consider a combinational circuit that computes the arithmetic function Z = X3 + 3X2 + 3X, where X is an n-bit unsigned number and Z is a 3n-bit unsigned number.

1. How many X values will cause an overflow?

2. Compute the logic equation for Z0  (The least significant bit of Z)?

3. Write a Verilog model for the above circuit for the case of n = 8.

1. The maximum value for Xis Xmax   =  2n – 1 . So, the maximum value of Z is

2. If Xis odd, then Z is odd. Hence, X0   =  1     →   Z0   =  1 .

3. Below is the best answer.