代做ECE-GY 9423: Design and Analysis of Communication Circuits and Components (Fall 2024) Homework # 3

ECE-GY 9423: Design and Analysis of Communication Circuits and Components

(Fall 2024)

Homework # 3 (Due on Tuesday, October 8th, 2024 before 11:59 pm EST.)

HW: All your calculations should have parametric expressions (wherever possible) and numerical answers (wherever required).

Problem 1 (On-chip wire modeling):

In a typical 180-nm technology node, the sheet resistance for metal1 (M1) and metal6 (M6) are 0.08 and 0.02Ω/⊡, respectively. The design rules do not allow a width smaller than 0.22μm for M1.

a)  Assuming a wire length of 1mm, draw an RC equivalent circuit for both M1 and M6 metals with minimum allowable width based on a 3-segment pi-model. (10 pts)

b)  Refer to the Cadence tutorial posted on the course website and set up a symbol for the pi- model networks that receives the length in millimeter as an input and adjusts the resistance/capacitance of the model, accordingly. You can use the following command to define the value of a component in a parametric way: pPar(“L”).   Include screenshots of M1 and M6 model.  (10 pts)

Problem 2 (Threshold Voltage and Body Effect in CMOS Transistors):

You are working as a design engineer for an integrated circuit company. One of your tasks is to analyze the behavior. of an NMOS transistor in a CMOS technology process where the body effect could significantly impact circuit performance.

Consider an NMOS transistor with the following parameters:

•    Threshold voltage without body effect, VT0: 0.4 V

•    Body effect coefficient, γ: 0.5 √v

•     Surface potential at inversion, 2ϕf  : 0.7 V

P1. Threshold Voltage with Different VSB : The threshold voltage of the NMOS transistor can be influenced by the source-to-bulk voltage VSB  due to the body effect. The equation governing the body effect is:

(a) Calculate the threshold voltage for VSB=0 V (nobody effect) (5pts)

(b) Calculate the threshold voltage when VSB=0.5V (5pts)

(c) Calculate the threshold voltage when VSB= 1. (5pts)

Comment on the impact of VSB  on the threshold voltage.

P1.  Cadence  Simulation. In  a  commercial  design  kit,  transistors  are  typically  offered  with various level of doping of the layer below the gate oxide to achieve different threshold voltages. In this part, we will simulate the body effect impact and process variation on the threshold voltage. Set up a testbench in Cadence and instantiate three NMOS devices with the following dimensions:

a) For VB = 0 (no body effect), plot the drain current of the transistors when the supply voltage is fixed at 1.2V and VG is changed from 0 to 1.2. Based on the results, estimate the threshold voltages and compare the values. (15pts)

b) What transistor would you pick if you wanted to  design  a high-speed inverter? How about a low-power amplifier? (5pts)

c) To observe the body effect, let’s focus on nmos1v device only. Plot the drain current versus the gate voltage for VB=0:0.5:1 and show the results. Comment on the impact of VB on the threshold voltage (5pts)

d) For the nmos1v_nat device, plot the drain current versus the supply voltage when it is changed from 0 to 1.2 with a VG = 0.7V. without changing the dimension ratio of the transistor (W/L), repeat the process for channel length of 900nm, and 2.7um.  Based on the results, estimate the   Early voltage (channel-length modulation). Comment on how the Early voltage is changed as the channel lengh is scaled. (15 pts)

Problem 3 (Transistor Operation Modes):

For the following circuits plot Vout versus Vin (changing from 0 to 3V) and identify the operating mode of the CMOS transistor. Assume that VTH, N  = 0.6V and |VTH, P | = 0.7V (30 pts)