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- 首页 >> Python编程 Lab 1 CMOS Inverter (100 pts)
The objective of this lab is to design an inverter with symmetric output rise and fall times (matched within
5%) and minimal Area-Delay Product (ADP). 10 points will be assigned based on the ranking of your
ADP (refer to point 3 in Section D).
Environment temperature of 85 ℃ and Vdd = 1.1V will be used throughout this project.
Section A: Schematic and Symbol (10 pts)
1. [8pt] In this section, please follow the tutorial to draw the schematic of an inverter. The devices we are
using are PMOS_VTG and NMOS_VTG in the library NCSU_Devices_FreePDK45. You have to choose
the size of the transistors. The inverter should fit all the following requirements: ● It has symmetric
output rise and fall times (matched within 5%)
● Pin names: VDD, GND, IN, OUT (all uppercase)
In DC analysis, find and label the point VM where Vin = Vout
. What do you expect the ratio to be between
VM and Vdd when the output rise/fall times are symmetric?
By varying the (W/L)p and (W/L)n ratio, you can change the DC operating point. Please choose the values
carefully. You are going to draw the layout with the same transistor size, and part of the score will be
evaluated by the Area-Delay Product. Explain the reasons behind your decisions. We expect you to
apply some theoretical analysis here (you can refer to related slides to facilitate theoretical analysis) to
derive the proper ratios, and do not solely rely on trial and error with simulations.
Figure 1. Inverter Schematic Example2. [2pt] Follow the same tutorial to create a symbol view for your inverter. Please use the standard
inverter symbol instead of a generic symbol like rectangle boxes.
Section B: Schematic Simulation (15 pts)
1. [5pt] DC Analysis:
Plot the Vout-Vin curve of the inverter you created, sweeping input voltage from 0 to VDD (1.1V). Plot
the output and input voltages in the same graph.
• Find VM, the inverter switching threshold voltage.
• Label VIH, VIL, VOL, VOL. Calculate NMH and NML. Refer Section 2.5.3 in the textbook (p.91-92).
We have:
• VIH = minimum HIGH input voltage
• VIL = maximum LOW input voltage
• VOH = minimum HIGH output voltage
• VOL = maximum LOW output voltage
• NML = VIL – VOL
• NMH = VOH - VIH
Figure 2. Noise margin definitions
2. [5pt] Create a testbench schematic for transient analysis with the inverter you just created. Please use
the test bench setup as shown in the schematic of Figure 3. All six inverters in the testbench should be the
one you created (i.e. instantiate six identical copies of it) and their roles are:
● DUT (Device Under Test): your designed inverter, I2
● Fan-in: one inverter as the input driver, I1
● Fan-out: four inverters (I3 - I6) in parallel as the load (this is what we call a fan out of four)
● Final stage: each load capacitor of inverter has 100fF
Assign net labels for the input (VIN) and output (VOUT) pin of the DUT (The one inverter at the middle
stage) for measurements.2
Figure 3. Inverter Testbench Schematics
3. [5pt] Transient Response: Perform a transient analysis of your inverter. Change the testbench to
generate pulses as the input stimulus with the following setting:
Initial
voltage
Pulse
voltage
Delay time Rise time Fall time Pulse width Cycle time
0V 1.1V 100ps 10ps 10ps 500ps 1ns
Simulate the circuit for at least 2.2ns. Set Simulation temperature to 85 ℃. Plot the input and output
voltage of the DUT inverter on the same graph. Measure the propagation delay, rise time and fall time of
the output signal.Section C: Inverter Layout (35 pts)
1. [20pt] Inverter Layout
Follow the tutorial to draw the layout of an inverter. Attach a screenshot of your layout, along with rulers
showing the width and height of its bounding box. Please note that we prefer smaller areas, but you must
follow all the design rules.
2. [5pt] Design Rule Check (DRC)
Attach a screenshot proving you have passed the DRC.
3. [5pt] Layout vs. Schematic (LVS)
Attach a screenshot proving you have passed the LVS.
4. [5pt] Extraction of Parasitic Capacitance (PEX)
Attach a screenshot of the parasitic view of the inverter.
Section D: Layout Simulation (40 pts)
1. [5pt] DC Analysis:
Perform the DC analysis of your inverter using the extracted view. Label VIH, VIL, VOL, VOL. Calculate
NMH and NML. (Please note that you do not have to design another testbench. Create a “config” cell view
for the one in part III. Adjust the configuration to choose the extracted view, and then launch ADE L
inside the config view in order to simulate with the extracted parasitics.)
2. [10pt] Transient Response:
Perform transient analysis using the extracted view (on allsix inverters in the testbench) using the
schematic shown in Figure 4. Simulation temperature: 85 ℃.. Plot the input and output voltage curves in
the same graph. Measure the propagation delay, rise time, and fall time.
3. [15pt] ADP In-class Ranking:
Please provide the area-delay product as defined below:
• ADP = bounding box area (nm2
) * delay (ps)
• delay = the average tpd of the largest delay of the first two cycles, i.e. (largest of tpdr1, tpdf1
, tpdr2
, tpdf2
)
The points you get depends on your ADP ranking in the class:
• Rank A, #1~#11: 10pts
• Rank B, #12~#21: 8pts
• Rank C, #22~#31: 6pts
• Rank D, #32~#41: 4pts
• Rank E, #42~51: 2pts
If the output rise/fall time difference is larger than 5%, 2 pts will be deducted from this part for every 5%.
4. [10pt] Compare the post-layout simulation result with that of the pre-layout (schematic) simulation. Do
you see any differences? Explain your findings and what are their implications for future layout projects?Submission
Please submit a report written in IEEE double-column conference format, following the template file
from Canvas. You can find the doc document under Files named IEEE_Template.
Please also submit a tgz file of your library (including inverter design and testbench cell views) along
with the written report to Canvas.
1) Go to the directory where you can see your library folder.
2) tar -czvf inverter_PID.tgz name-of-your-library
Please replace PID with your PID and the name of your virtuoso library as name-of-your-library. For
example, if your PID is andrew123, and your virtuoso library name for the assignment is lab1, then the
command should be:
tar -czvf inverter_andrew123.tgz lab1
And you should submit the file named inverter_andrew123.tgz and the written report in pdf (as two file
uploads in canvas).
Hint:
If you're using ssh.ece.vt.edu to access the software, you can use key
combination to bring out Guacamole Menu, where you can upload and download files from the remote
server by drag and drop.
The objective of this lab is to design an inverter with symmetric output rise and fall times (matched within
5%) and minimal Area-Delay Product (ADP). 10 points will be assigned based on the ranking of your
ADP (refer to point 3 in Section D).
Environment temperature of 85 ℃ and Vdd = 1.1V will be used throughout this project.
Section A: Schematic and Symbol (10 pts)
1. [8pt] In this section, please follow the tutorial to draw the schematic of an inverter. The devices we are
using are PMOS_VTG and NMOS_VTG in the library NCSU_Devices_FreePDK45. You have to choose
the size of the transistors. The inverter should fit all the following requirements: ● It has symmetric
output rise and fall times (matched within 5%)
● Pin names: VDD, GND, IN, OUT (all uppercase)
In DC analysis, find and label the point VM where Vin = Vout
. What do you expect the ratio to be between
VM and Vdd when the output rise/fall times are symmetric?
By varying the (W/L)p and (W/L)n ratio, you can change the DC operating point. Please choose the values
carefully. You are going to draw the layout with the same transistor size, and part of the score will be
evaluated by the Area-Delay Product. Explain the reasons behind your decisions. We expect you to
apply some theoretical analysis here (you can refer to related slides to facilitate theoretical analysis) to
derive the proper ratios, and do not solely rely on trial and error with simulations.
Figure 1. Inverter Schematic Example2. [2pt] Follow the same tutorial to create a symbol view for your inverter. Please use the standard
inverter symbol instead of a generic symbol like rectangle boxes.
Section B: Schematic Simulation (15 pts)
1. [5pt] DC Analysis:
Plot the Vout-Vin curve of the inverter you created, sweeping input voltage from 0 to VDD (1.1V). Plot
the output and input voltages in the same graph.
• Find VM, the inverter switching threshold voltage.
• Label VIH, VIL, VOL, VOL. Calculate NMH and NML. Refer Section 2.5.3 in the textbook (p.91-92).
We have:
• VIH = minimum HIGH input voltage
• VIL = maximum LOW input voltage
• VOH = minimum HIGH output voltage
• VOL = maximum LOW output voltage
• NML = VIL – VOL
• NMH = VOH - VIH
Figure 2. Noise margin definitions
2. [5pt] Create a testbench schematic for transient analysis with the inverter you just created. Please use
the test bench setup as shown in the schematic of Figure 3. All six inverters in the testbench should be the
one you created (i.e. instantiate six identical copies of it) and their roles are:
● DUT (Device Under Test): your designed inverter, I2
● Fan-in: one inverter as the input driver, I1
● Fan-out: four inverters (I3 - I6) in parallel as the load (this is what we call a fan out of four)
● Final stage: each load capacitor of inverter has 100fF
Assign net labels for the input (VIN) and output (VOUT) pin of the DUT (The one inverter at the middle
stage) for measurements.2
Figure 3. Inverter Testbench Schematics
3. [5pt] Transient Response: Perform a transient analysis of your inverter. Change the testbench to
generate pulses as the input stimulus with the following setting:
Initial
voltage
Pulse
voltage
Delay time Rise time Fall time Pulse width Cycle time
0V 1.1V 100ps 10ps 10ps 500ps 1ns
Simulate the circuit for at least 2.2ns. Set Simulation temperature to 85 ℃. Plot the input and output
voltage of the DUT inverter on the same graph. Measure the propagation delay, rise time and fall time of
the output signal.Section C: Inverter Layout (35 pts)
1. [20pt] Inverter Layout
Follow the tutorial to draw the layout of an inverter. Attach a screenshot of your layout, along with rulers
showing the width and height of its bounding box. Please note that we prefer smaller areas, but you must
follow all the design rules.
2. [5pt] Design Rule Check (DRC)
Attach a screenshot proving you have passed the DRC.
3. [5pt] Layout vs. Schematic (LVS)
Attach a screenshot proving you have passed the LVS.
4. [5pt] Extraction of Parasitic Capacitance (PEX)
Attach a screenshot of the parasitic view of the inverter.
Section D: Layout Simulation (40 pts)
1. [5pt] DC Analysis:
Perform the DC analysis of your inverter using the extracted view. Label VIH, VIL, VOL, VOL. Calculate
NMH and NML. (Please note that you do not have to design another testbench. Create a “config” cell view
for the one in part III. Adjust the configuration to choose the extracted view, and then launch ADE L
inside the config view in order to simulate with the extracted parasitics.)
2. [10pt] Transient Response:
Perform transient analysis using the extracted view (on allsix inverters in the testbench) using the
schematic shown in Figure 4. Simulation temperature: 85 ℃.. Plot the input and output voltage curves in
the same graph. Measure the propagation delay, rise time, and fall time.
3. [15pt] ADP In-class Ranking:
Please provide the area-delay product as defined below:
• ADP = bounding box area (nm2
) * delay (ps)
• delay = the average tpd of the largest delay of the first two cycles, i.e. (largest of tpdr1, tpdf1
, tpdr2
, tpdf2
)
The points you get depends on your ADP ranking in the class:
• Rank A, #1~#11: 10pts
• Rank B, #12~#21: 8pts
• Rank C, #22~#31: 6pts
• Rank D, #32~#41: 4pts
• Rank E, #42~51: 2pts
If the output rise/fall time difference is larger than 5%, 2 pts will be deducted from this part for every 5%.
4. [10pt] Compare the post-layout simulation result with that of the pre-layout (schematic) simulation. Do
you see any differences? Explain your findings and what are their implications for future layout projects?Submission
Please submit a report written in IEEE double-column conference format, following the template file
from Canvas. You can find the doc document under Files named IEEE_Template.
Please also submit a tgz file of your library (including inverter design and testbench cell views) along
with the written report to Canvas.
1) Go to the directory where you can see your library folder.
2) tar -czvf inverter_PID.tgz name-of-your-library
Please replace PID with your PID and the name of your virtuoso library as name-of-your-library. For
example, if your PID is andrew123, and your virtuoso library name for the assignment is lab1, then the
command should be:
tar -czvf inverter_andrew123.tgz lab1
And you should submit the file named inverter_andrew123.tgz and the written report in pdf (as two file
uploads in canvas).
Hint:
If you're using ssh.ece.vt.edu to access the software, you can use
combination to bring out Guacamole Menu, where you can upload and download files from the remote
server by drag and drop.